A processing core can include multiple data processors that execute program instructions by performing various arithmetic operations. Examples of arithmetic operations that can be performed by a data processor (such as, for example, a CPU, GPU or combined CPU and GPU often referred to as accelerated processing units (APUs), and the like) include addition, multiplication, division, and the like. In addition, some processors can support more complex operations. For instance, one example is a multiply-and-accumulate (MAC) operation that computes the product of two numbers and adds that product to another number.
One conventional type of multiplier module includes booth encoder circuitry that is used to process a multiplier operand and generate control signals that are provided to corresponding booth multiplexers. The booth multiplexers use these control signals to process the multiplicand operand and generate partial products that are then provided to a compression tree. The compression tree includes a carry-save adder (CSA) array and a carry-save adder (CSA) coupled to the CSA array. The CSA array has inputs configured to receive the partial products, and includes a number of carry save adders (CSAs) implemented at different compressor levels for compressing the partial products to generate a sum and carry output.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.